2026
SSCL
A Sampling PLL with Boosted Phase Detection Gain Achieving 52 fs RMS Jitter and 110.4 MHz Lock-in Range
IEEE Solid-State Circuits Letters (SSC-L), Accepted for publication
H. An, C. An, S. Kim, and H. Yoon*
JETCAS
A Neuromorphic Image Sensor with In-Sensor Spiking Neural Network Computing
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, Accepted for publication
J. Hwang, J. Kim, J. Kang, K. Hong, H. Yoon, and S. Kim*
TCAD
A Framework of Automated LC-VCO Design with Physical Layout Based on Reinforcement Learning
IEEE Computer-Aided Design of Integrated Circuits and Systems (TCAD), Accepted for publication
S. Kim, H. Lee, S. Hong, H. Yoon*, and T. Song*
JSSC
A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator
IEEE Journal of Solid-State Circuits (JSSC), Accepted for publication
H. Nam, H. An, C. An, S. Kim, and H. Yoon*
ISSCC SRP
A Dual-Slope Sampling PLL with Boosted Phase Detection Gain and Wide Lock-in Range Achieving 52 Fs RMS Jitter
IEEE International Solid-State Circuits Conference (ISSCC) SRP session
H. An, C. An, S. Kim, and H. Yoon*
JSSC
A −53.7 dB PSRR, Fast-Transient Output-Capacitor-less Digital-Assisted Analog LDO Using Seamless Digital-to-Analog Transfer Technique
IEEE Journal of Solid-State Circuits (JSSC), Accepted for publication
C. An, H. An, H. Nam, and H. Yoon*
TCAS-I
A Multibit ReRAM Computing-in-Memory Processor with Adaptive Decision Level Nonlinear ADC for Ultra-low-energy Keyword Spotting in Mobile Devices
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), Accepted for publication
D. Kim, H. Jeong, S. Kim, H. Yoon*, and K. J. Lee*
2025
A-SSCC
An area-efficient, DTC-Less fractional-N Sampling PLL Achieving 140 fs RMS Jitter and −66.3 dBc Fractional Spur
IEEE Asian Solid-State Circuits Conference, Nov. 2025
H. An, H. Nam, C. An, and H. Yoon*
Sensors Journal
A Mixture-Gas Multisensor Interface with On-chip Classification and On-Edge Regression
IEEE Sensors Journal, vol. 25, no. 16, pp. 31435-31446, 15 Aug. 2025
Y. Kim, J. Cho, Y. Pyeon, H. Kim, S. Lee, J. Kwak, H. Yoon, Y. Lee, and J. Kim
SSC-L
A 6.2b-ENOB 2.5GS/s Flash-and-VCO Based Subranging ADC Using a Residue Shifting Technique
IEEE Solid-State Circuits Letters (SSC-L), vol. 8, pp. 177-180, 2025
S. Kim=, J. Lee=, Y. Cho, J. Kim, J. Choi*, and H. Yoon* (=Equal-Credited Author)
JSSC
A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer with a Subsampling PLL and a Harmonic Boosting Frequency Multiplier
IEEE Journal of Solid-State Circuits (JSSC), vol.60, no. 5, pp. 1632-1643, May 2025.
S. Jung, J. Kim, J. Bang, S. Lee, H. Yoon*, and J. Choi*
TCAS-II
An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors
IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 72, no. 1, pp. 143-147, Jan. 2025
H. An, H. Nam, S. Kim, Y. Lim, and H. Yoon*
2021
ISSCC
An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS
IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2021
S. Yoo=, S. Park=, S. Choi=, Y. Cho, H. Yoon, C. Hwang, and J. Choi (=Equal-Credited Author)
2020
ISSCC
A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator
IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2020
Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, and J. Choi (=Equal-Credited Author)
2019
JSSC
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators
IEEE Journal of Solid-State Circuits (JSSC), vol.54, no. 12, pp. 3466-3477, Dec. 2019.
J. Kim, Y. Lim, H. Yoon, Y. Lee, Y. Cho, T. Seong, and J. Choi
JSSC
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration
IEEE Journal of Solid-State Circuits (JSSC), vol.54, no. 6, pp. 1564-1574, Jun. 2019.
H. Yoon, S. Park, and J. Choi
ISSCC
A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2019
J. Kim=, H. Yoon=, Y. Lim*, Y. Lee, Y. Cho, T. Seong, and J. Choi (=Equal-Credited Author)
2018
ISSCC
Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers
IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2018
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi
JSSC
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers
IEEE Journal of Solid-State Circuits (JSSC), vol.53, no. 2, pp. 375-388, Feb. 2018.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi
ASP
DAC
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers
IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2018
S Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi
2017
ASSCC
An Ultra-Low Phase Noise All-Digital Multi-Frequency Generator Using Injection-Locked DCOs and Time-Interleaved Calibration
IEEE Asian Solid-State Circuits (ASSCC), Nov. 2017
S. Park, H. Yoon, and J. Choi
ISSCC
A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop for mm-Band 5G Transceivers
IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2017
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi
2016
VLSI
A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop
IEEE VLSI Symposium, Jun. 2016
Y. Lee, H. Yoon, M. Kim, and J. Choi
JSSC
A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers
IEEE Journal of Solid-State Circuits (JSSC), vol.51, no. 3, pp. 614-625, Mar. 2016
H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi
2014
TCAS-II
A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core
IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 61, no. 5, pp. 289-293, May 2014
H. Yoon, Y. Lee, and J. Choi
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